1. Field of the Invention
The present invention generally relates to semiconductor memory devices including a redundant cell array, and particularly relates to a semiconductor memory device including a redundant cell array having an improved efficiency of redundancy processing.
2. Description of the Related Art
Redundant cells are indispensable technology in semiconductor memory devices such as DRAMs (dynamic random access memories). As technology for increasing circuit density advances, many numbers of deficient cells are generated at incipient stages of related technologies. In such cases, deficient cells need to be replaced by numbers of redundant cells and redundancy circuits. As these technologies mature, however, the number of deficient cells decreases, resulting in the redundant cells being wasted as they are provided in excess numbers to meet the strong demand at the incipient stages. This means an increase of unusable and wasted chip areas.
As is pointed out above, many numbers of redundancy circuits are necessary at incipient stages of new technologies, but will be wasted as these technologies mature.
In conventional redundancy circuits, fuses are cut so that these fuses correspond to addresses of deficient bits, words, column selection lines, data bus lines, etc. When access to these addresses is attempted, the access is directed to redundant cells that have replaced the deficient elements.
Such a configuration is permanently fixed once the fuses are cut regardless of whether row redundancy or column redundancy is employed. In the case of column redundancy, for example, when a deficient column is replaced by a redundant cell array, any access to this column is treated as access to the redundant cell array without exception. In order to provide a redundancy mechanism for two columns, therefore, such a redundancy mechanism needs to have twice the size the redundancy mechanism for one column. This results in an increase of chip size.
Accordingly, there is a need for a semiconductor memory device which can cope with larger numbers of deficiencies without increasing the size of a redundant cell array by improving efficiency of redundancy operation.
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor memory device including a fuse circuit which indicates a defective portion in a row direction, and also indicates the defective portion in a column direction, and a control circuit which switches data buses to avoid the defective portion indicated in the column direction by the fuse circuit when the defective portion indicated in the row direction by the fuse circuit corresponds to a row address that is input to the semiconductor memory device.
In the device as described above, the fuses specify the defective portion in the row direction and in the column direction, and it is decided based on the row address of access operation whether to switch to redundant cells, i.e., whether to engage in column redundancy operation. This achieves efficient redundancy processing.